fbpx New Content Addressable Memory Architecture for Multi-Core Applications |ARAB AMERICAN UNIVERSITY
Contact information for Technical Support and Student Assistance ... Click here

New Content Addressable Memory Architecture for Multi-Core Applications

Chapter Number: 
5
Authors: 
Mahmoud Obaid
Allam Abumwais
Book Title: 
Computer Memory and Data Storage
Publisher: 
intechopen
ISBN: 
978-1-80355-589-8
Date: 
Friday, December 15, 2023
Abstract: 
The future of massively parallel computation appears promising due to the emergence of multi- and many-core computers. However, major progress is still needed in terms of the shared memory multi- and many-core systems, specifically in the shared cache memory architecture and interconnection network. When multiple cores try to access the same shared module in the shared cache memory, issues arise. Cache replacement methods and developments in cache architecture have been explored as solutions to this. This chapter introduces the Near-Far Access Replacement Algorithm (NFRA), a new hardware-based replacement technique, as well as a novel dedicated pipeline cache memory design for multi-core processors, known as dual-port content addressable memory (DPCAM). The experiments show that the access latency for write/read operations of a DPCAM is lower than that of a set-associative (SA) cache memory, with the latency of a write operation staying the same regardless of the size of the DPCAM. It is estimated that the power usage will be 7% greater than a SA cache memory of the same size.